This invention relates to semiconductor devices, and more particularly to methods of making CMOS circuits of the type used in VLSI dynamic memory devices or the like.
Dynamic read/write memory devices of the type shown in U.S. Pat. No. 4,239,993, issued to McAlexander, White and Rao, assigned to Texas Instruments, have been manufactured by N-channel, self-aligned, silicon gate processes as disclosed in U.S. Pat. No. 4,055,444 or U.S. Pat. No. 4,240,092, for example. Requirements for low power have led to more widespread use of CMOS processing as in U.S. Pat. No. 4,295,897, for example, and further the higher densities in 256K-bit or 1-Megabit dynamic RAMs have necessitated the use of smaller device geometries, presenting problems of alignment, step coverage, undercutting, etc. A twin-well CMOS process employing field-plate isolation, and buried N+ source/drain regions and bit lines, suitable for 1-Mbit sized memory arrays, is illustrated in copending application Ser. No. 626,572 filed July 2, 1984, by Doering and Armstrong, assigned to Texas Instruments.
It is the principal object of this invention to provide improved and simplified methods of making integrated circuits for semiconductor memory devices or the like, particularly low-power, high-density devices. Another object is to provide improved CMOS processes as may be used for making high density dynamic RAMs.